The present invention is a circuit for performing high speed division having particular application when high speed address calculation is needed, for example, where a new address is required in single clock cycle. An example of an application where high speed division operations is desirable is processing of data representing images for display on a color monitor. In the prior art, division is typically implemented as a succession of subtract and shift operations. Descriptions of prior art subtract and shift circuits may be found in U.S. Pat. No. 5,012,439; ."Division: Part IV", IEEE Computer Society Press; Computer Arithmetic; Vol. I, 1990, pp. 156-194. A faster method utilizes parallel processing of each quotient bit as described in U.S. Pat. No. 4,935,892. However, the circuitry required to implement the teachings of this patent is massive, and is still too slow.